1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device including an internal power circuit having a tuning function by using a fuse device or the like.
2. Description of the Background Art
In the field of data process and the like, to process data at high speed with lower power consumption, a circuit device called a system LSI (Large Scale Integrated circuit) in which a logic such as a processor and a memory device are integrated on the same semiconductor chip is widely used. In the system LSI, the logic and the memory device are connected to each other by wiring on the chip, so that multi-bit data can be transferred between the logic and the memory device at high speed.
FIGS. 7A and 7B are diagrams for explaining a conventional layout of an internal power circuit in a semiconductor memory device.
Referring to FIG. 7A, a semiconductor memory device 1 has memory arrays 2a and 2b, a decoder band 3, and an internal power circuit 4. Via external pads 5, external signals are transmitted/received to/from semiconductor memory device 1 mounted on a system LSI, and an external source voltage is supplied to semiconductor memory device 1. External pads 5 includes a power source pad 5a for receiving the supply of an external source voltage Ext.VDD and a signal pad 5b via which signals are transmitted/received to/from the outside.
FIG. 7B is an enlarged view of an area 50 shown in FIG. 7A, in which fuse devices FS and internal wiring are disposed.
A plurality of memory cells arranged in a matrix for storing data and peripheral circuits for reading/writing data from/to the memory cells are generically called as memory arrays 2a and 2b. 
Decoder band 3 decodes a command control signal and an address signal supplied via signal pad 5b. Internal power circuit 4 receives external source voltage Ext.VDD supplied from the outside via power source pad 5a and generates internal source voltages for operating memory arrays 2a and 2b. 
FIG. 8 is a schematic block diagram showing the configuration of internal power circuit 4.
Referring to FIG. 8, internal power circuit 4 includes a reference voltage generating unit 10, a memory array voltage (VDDS) generating circuit 20, a boosted voltage (VPP) generating circuit 30, and a negative voltage (VBB) generating circuit 40. Memory array voltage (VDDS), boosted voltage (VPP), and negative voltage (VBB) are collectively called the internal source voltages.
Reference voltage generating unit 10 includes reference voltage generating circuits 12 and 14. Reference voltage generating circuit 12 receives external source voltage Ext.VDD and generates a reference voltage VREFS as a reference value of memory array voltage VDDS. Reference voltage generating circuit 14 receives external source voltage Ext.VDD and generates a reference voltage VREFP as a reference value of boosted voltage VPP. For example, 3.3V is applied as external source voltage Ext.VDD.
Memory array voltage generating circuit 20 includes a voltage comparator 22 and a driver transistor 25, and controls the voltage level of an internal power line 27 for supplying memory array voltage VDDS in accordance with reference voltage VREFS. For example, memory array voltage VDDS is set to 2.0 V.
Voltage comparator 22 compares memory array voltage VDDS with reference voltage VREFS. Driver transistor 25 is electrically connected between external source voltage Ext.VDD and internal power line 27 and receives an output of voltage comparator 22 by its gate.
Concretely, when memory array voltage VDDS drops below reference voltage VREFS (2.0 V), an output of voltage comparator 22 is activated to the xe2x80x9cL level (logic low)xe2x80x9d and driver transistor 25 is turned on. Consequently, an operation current is supplied from external source voltage Ext.VDD to internal power line 27. On the other hand, when memory array voltage VDDS is higher than reference voltage VREFS, an output of voltage comparator 22 is made inactive to the xe2x80x9cH level (logic high)xe2x80x9d. In response to this, driver transistor 25 is turned off. As a result, the supply of the operation current to internal power line 27 is stopped.
Boosted voltage generating circuit 30 receives external source voltage Ext.VDD and generates boosted voltage VPP based on reference voltage VREFP. Boosted voltage VPP is used as a gate voltage for turning on a transistor provided to transmit H-level data (memory array voltage VDDS) to a memory cell. It is therefore necessary to set boosted voltage VPP to a voltage higher than a sum of memory array voltage VDDS and a threshold voltage Vth of the transistor. For example, boosted voltage VPP is set to 3.6V.
Boosted voltage generating circuit 30 includes: a voltage divider 32 for dividing a voltage of an internal power line 31 for transmitting boosted voltage VPP; a detecting circuit 34 for comparing voltage VDPP obtained by the dividing operation of voltage divider 32 with reference voltage VREFP; an oscillator 35 which is set in an operative state in accordance with a result of detection of detecting circuit 34 to generate a pump clock; and a charge pump circuit 36 for executing boosting operation in response to the pump clock generated by oscillator 35.
Voltage divider 32 divides the voltage of internal power line 31 to, for example, xc2xd and outputs divided voltage VDPP. Detecting circuit 34 receives reference voltage VREFP (1.8 V) determined in consideration of the reference value of boosted voltage VPP and the voltage dividing ratio in voltage divider 32. When the divided voltage VDPP drops below reference voltage VREFP, oscillator 35 is set in the operative state.
In the operative state, oscillator 35 generates a pump clock and supplies it to charge pump circuit 36. Charge pump circuit 36 performs charge pumping operation on the basis of the pump clock from oscillator 35 to boost external source voltage Ext.VDD, thereby generating boosted voltage VPP. On the other hand, when boosted voltage VPP is higher than the reference value, oscillator 35 is set in an inoperative state to stop the generation of the pump clock. The voltage boosting operation by charge pump circuit 36 is not therefore executed.
Negative voltage generating circuit 40 receives external source voltage Ext.VDD and generates negative voltage VBB. Negative voltage VBB is used to suppress a leak current in an access transistor of a memory cell. For example, negative voltage VBB is set to xe2x88x921.0 V.
Negative voltage generating circuit 40 includes a detecting circuit 44, an oscillator 45, and a charge pump circuit 46. When the voltage level of an internal power line 41 for supplying negative voltage VBB exceeds xe2x88x921.0 V as a reference value, detecting circuit 44 sets oscillator 45 to an operative state.
In an operative state, oscillator 45 supplies the pump clock to charge pump circuit 46. Charge pump circuit 46 executes a negative charge pump operation on the basis of the pump clock from oscillator 45 to supply negative charges to internal power line 41. On the other hand, when negative voltage VBB is lower than a reference voltage xe2x88x921.0 V, oscillator 45 is set in an inoperative state to stop generation of the pump clock. As a result, the supply of negative charges by charge pump circuit 46 is stopped.
With such a configuration, the internal source voltages of memory array voltage VDDS, boosted voltage VPP, and negative voltage VBB can be controlled so as to coincide with reference values.
Since the internal source voltages exert a great influence on the data retaining characteristic of a memory cell and access characteristic, high control accuracy is required. Before the manufacturing stage, an internal power circuit is designed so that the internal source voltages become at desired levels. However, an actually fabricated chip is influenced by manufacture process variations, so that a desired internal source voltage level cannot be always output by the internal power circuit. There is also a case that the internal source voltage level has to be changed due to an influence of manufacture variations in a memory array.
Consequently, a configuration of providing the internal power circuit with a tuning function by using a program device such as a fuse is generally employed. For example, in the configuration of FIG. 8, to accurately set or finely adjust the levels of reference voltages VREFS and VREFP in reference voltage generating circuits 12 and 14, or to accurately set or finely adjust xe2x88x921.0 V corresponding to the reference value of negative voltage VBB in the detecting circuit 44, the tuning function is used.
A concrete configuration of a circuit group having the tuning function will now be described.
FIG. 9 is a circuit diagram showing the configuration of reference voltage generating circuit 12 for memory array voltage VDD.
Referring to FIG. 9, reference voltage generating circuit 12 includes current source 50 disposed between a node Ns for generating reference voltage VREFS and external source voltage Ext.VDD, for supplying a constant current Is, P-channel MOS transistors 51 to 55, 57, and 58 connected in series between node Ns and a ground voltage VSS, and fuse devices FS1s to FS4s. 
The gates of transistors 51 to 55 and 58 are connected to ground voltage VSS. Transistor 57 is connected so as to form a diode. A voltage drop caused by transistors 57 and 58 therefore becomes 2Vth corresponding to twice as high as threshold voltage Vth of the transistor.
Fuse devices FS1s to FS4s are connected in parallel with transistors 51 to 54, respectively. Since transistors 51 to 55 and 57 whose gates are connected to ground voltage VSS act as resistive elements, in a conductive state before each of fuse devices FS1s to FS4s is blown, each of fuse devices FS1s to FS4s forms a bypass of a corresponding transistor acting as a resistive element.
On the other hand, the fuse device shifted to a nonconductive state by being blown closes the bypass, so that constant current Is is passed to the corresponding transistor (resistive element).
As described above, an electrical resistance value RS to be added to the current path of constant current Is is finely adjusted according to the states of fuse devices FS1s to FS4s. The voltage level of reference voltage VREFS generated at node Ns changes depending on electrical resistance value RS between nodes Ns and N0. Consequently, by selectively blowing (disconnecting) fuse devices FS1s to FS4s, reference voltage VREFS can be finely adjusted.
FIG. 10 is a circuit diagram showing the configuration of reference voltage generating circuit 14 for boosted voltage VPP.
Referring to FIG. 10, reference voltage generating circuit 14 includes a current source 60 disposed between a node Np for generating reference voltage VREFP and external source voltage Ext.VDD, for supplying a constant current Is, P-channel MOS transistors 61 to 65, 67, and 68 connected in series between node Np and ground voltage VSS, and fuse devices FS1p to FS4p. 
Reference voltage generating circuit 14 has a configuration similar to that of reference voltage generating circuit 12 shown in FIG. 9 but an electrical resistance value RP between nodes Np and N1 is set independently of electrical resistance value RS in FIG. 8. In a manner similar to reference voltage generating circuit 12, by selectively blowing fuse devices FS1p to FS4p, reference voltage VREFP corresponding to the reference value of boosted voltage VPP can be finely adjusted.
FIG. 11 is a circuit diagram showing the configuration of detecting circuit 44.
Referring to FIG. 11, detecting circuit 44 includes: a current source 70 connected between external source voltage Ext.VDD and a node Na; an N-channel MOS transistor 71 connected between node Na and ground voltage VSS; a P-channel MOS transistor 72 electrically connected between external source voltage Ext.VDD and a node Nb; a P-channel MOS transistor 73 electrically connected between external source voltage Ext.VDD and a node Nc; an N-channel MOS transistor 74 electrically connected between nodes Nb and Nv; an N-channel MOS transistor 75 electrically connected between node Nc and ground voltage VSS; and a buffer 76 for outputting a detection signal on the basis of a voltage of node Nc.
A detection signal output from buffer 76 is transmitted to oscillator 45 shown in FIG. 7. The gates of transistors 71, 74, and 75 are connected to node Na. The level of the voltage of node Nc, that is, a detection signal is determined according to a voltage difference between ground voltage VSS and a node Nv corresponding to a virtual ground node.
Detecting circuit 44 further includes N-channel MOS transistors 80 to 84 connected in series between a node Ni to which negative voltage VBB is supplied and node Nv and fuse devices FS1b to FS4b connected in parallel with transistors 81 to 84, respectively.
Each of the gates of transistors 80 to 84 is connected to ground voltage VSS. Each of transistors 80 to 84 acts as a resistive element. An electrical resistance value RB between nodes Nv and Ni can be finely adjusted by selectively blowing fuse devices FS1b to FS4b. 
When negative voltage VBB (for example, xe2x88x921.0 V) of the reference value is applied to node Ni, the voltage at node Nv has to be set to ground voltage VSS. Specifically, electrical resistance value RB is finely adjusted so that a voltage drop between nodes Nv to Ni is equal to the difference (for example, 1.0 V) between ground voltage VSS and the reference value of negative voltage VBB.
With such a configuration, when negative voltage VBB exceeds the reference value, the voltage at node Nv becomes higher than ground voltage VSS. The voltage at node Nc is accordingly changed to the ground voltage VSS side, and a detection signal is activated to the L level. In response to this, oscillator 45 generates a pump clock.
On the contrary, when negative voltage VBB does not exceed the reference value, node Nc changes to the Ext.VDD side and a detection signal is made inactive to the H level. In this case, oscillator 45 stops the supply of the pump clock.
By using the tuning function as described above, a desired internal source voltage can be generated in consideration of manufacture process variations.
Referring again to FIG. 7A, to minimize the voltage drop from power source pad 5a to internal power circuit 4 and supply the internal source voltage generated by internal power circuit 4 to memory arrays 2a and 2b with the minimum voltage drop, it is desirable to shorten the distance between the external pad and the memory array as much as possible. It is desirable to assure a sufficient line width for an internal line such as a power source line disposed in internal power circuit 4. From such a viewpoint, internal power circuit 4 is disposed so as to be elongated in the chip peripheral portion along memory arrays 2a and 2b as internal circuits.
The layout of reference voltage generating unit 10, memory array source generating circuit 20, boosted voltage (VPP) generating circuit 30, and negative voltage (VBB) generating circuit 40 shown in FIG. 8 is determined so as to be adjusted to the shape of internal source circuit 4.
As described with reference to FIGS. 8 to 11, in reference voltage generating unit 10 and VBB generating circuit 40, fuse devices for the tuning function are disposed. In FIG. 7A, fuse devices FS1s to FS4s, FS1p to FS4p, and FS1b to FS4b shown in FIGS. 9 to 11 are collectively referred to as fuse devices FS.
As the material of the fuse device, aluminum is typically used. An aluminum fuse is generally blown with a laser beam after a chip is fabricated.
However, since a laser blowing input (laser beam) is passed, another aluminum wiring layer cannot be disposed as an upper or lower layer of the fuse device. It is difficult to dispose an aluminum wiring layer used for a purpose other than a fuse also around the aluminum fuse so as not to be to damaged by the blowing with the laser beam.
By providing the fuse device in the internal power circuit desirably to have an elongated shape, the designing becomes difficult.
Referring again to FIG. 7B, in an area 50 in internal power circuit 4, power lines L1 and L2 have to be designed so as to bypass fuses FS and so that the line width is narrowed around fuse FS. In order to reduce wiring bypassing the fuse as much as possible, the layout of the function blocks has to be also regulated. Consequently, it becomes difficult to make a floor plan of the internal power circuit.
In the internal power circuit, a high-impedance signal line which has to be shielded like a signal line L3 exists. High-impedance signal line L3 is a line for transmitting reference voltage VREFP or VREFS shown in FIG. 8 to a VDDS generating circuit or the like. For such a high-impedance signal line, shielding wires LS1 and LS2 have to be disposed in an adjacent area. When the number of such layout restrictions increases, it is feared that electric characteristics deteriorate such that the shielding wires cannot be sufficiently disposed.
To solve such problems, it is sufficient to dispose the fuse devices independent of the power circuit layout or at an end of the power circuit layout. However, when the length of the line between the fuse and the internal power circuit is simply increased, the voltage level of the high-impedance signal line becomes unstable due to noises occurring on the line, so that it is feared that the control characteristics of the internal power circuit deteriorate.
As a method of disposing the fuse device in a position away from the power circuit, for example, the technique of Japanese Patent Laying-Open No. 11-233634(1999) has been disclosed. In the configuration disclosed in the publication, however, a fuse disposed in a position apart from the power circuit is provided for a test but not for realizing the tuning function in the internal power circuit. Therefore, by the technique disclosed in the publication, the problems as described above cannot be solved.
An object of the invention is to provide a semiconductor memory device including an internal power circuit having a tuning function, of which layout such as a floor plan and a wiring plan can be easily designed and of which circuit operation is stabilized.
A semiconductor memory device according to the invention includes an internal circuit operating on supply of an internal source voltage; and an internal power circuit for receiving an external source voltage and generating the internal source voltage. The internal power circuit includes: a plurality of internal lines; a plurality of program devices disposed in an area different from an area in which the plurality of internal lines are disposed and each shifting from a first state to a second state in response to a program input from the outside (external to said internal power circuit); a plurality of signal driving circuits provided in correspondence with the plurality of program devices and each for driving a control signal having a level according to the state of a corresponding one of the program devices; and an internal voltage generating circuit for adjusting the level of the internal source voltage on the basis of the control signal driven by each of the plurality of signal driving circuits.
In such a semiconductor memory device, a plurality of internal lines can be disposed flexibly without bypassing program devices disposed for realizing the tuning function while sufficiently assuring the line width. Thus, the designing of the internal power circuit is facilitated and the stabilized circuit operation can be realized.
Preferably, the internal voltage generating circuit has: a reference voltage generating unit for generating a reference voltage corresponding to a reference value of the internal source voltage; and an internal voltage driving unit for controlling the internal source voltage on the basis of comparison between the internal source voltage and the reference voltage, and the reference voltage generating unit adjusts the reference voltage on the basis of the control signal.
Preferably, the internal voltage generating circuit includes: a detecting unit for detecting that the internal source voltage exceeds a reference value; and an internal voltage driving portion for controlling the internal source voltage on the basis of a detection result of the detecting portion, and the detecting unit adjusts the reference value on the basis of the control signal.
Preferably, the semiconductor memory device further includes a power source pad for receiving supply of the external source voltage. The internal power circuit is disposed in an elongated shape between the internal circuit and the power source pad along an peripheral portion of the internal circuit.
With such a configuration, a voltage drop in an external source voltage and an internal source voltage can be suppressed.
Particularly, in the configuration, the program devices are disposed in a chip peripheral portion.
Alternately, in the configuration, the program devices are disposed in an end portion of the internal power circuit.
Preferably, a circuit device group constructed by the internal voltage generating circuit and the plurality of signal driving circuits is disposed on the inner side of the plurality of program devices in the chip along a longitudinal direction of the internal power circuit.
With the configuration, the lines and circuit devices disposed on the upper and lower areas of the fuse devices can be further reduced, and improved flexibility in designing can be achieved.
Preferably, the plurality of internal lines include a program device control line for transmitting signals for controlling current passage to the plurality of program devices, and a line group other than the program device control line in the plurality of internal lines is disposed on the inner side of the plurality of program devices of the chip along a longitudinal direction of the internal power circuit.
Preferably, the internal power circuit further includes a program device energization control circuit for controlling current passage to the plurality of program devices. Circuit elements as a components of the internal power circuit is disposed on the inner side of the plurality of program devices of the chip along a longitudinal direction of the internal power circuit except for a circuit device group constructing the program device energization control circuit.
Preferably, the internal power circuit further includes a program device energization control circuit for controlling current passage to the plurality of program devices, and circuit elements as components of the plurality of signal driving circuits and the program device energization control circuit are disposed in an area different from an area in which other circuit devices in the internal power circuit are disposed.
Preferably, the semiconductor memory device further includes: a signal pad for inputting/outputting signals from/to the internal circuit; and a signal line provided between the signal pad and the internal circuit, for transmitting the signal. The plurality of internal lines are disposed without crossing the signal line.
With such a configuration, the tuning function in the internal power circuit can be displayed while further increasing noise resistance.
More preferably, the program devices are disposed at both ends in the longitudinal direction of the internal power circuit.
More preferably, alternately, the program devices are disposed only at one end in the longitudinal direction of the internal power circuit.
Preferably, the internal circuit includes a memory array portion including a plurality of memory cells for storing data and peripheral circuits for reading/writing data from/to the plurality of memory cells.
Consequently, by using the internal power circuit which can be easily designed, a voltage used in the memory array portion can be finely adjusted.
Preferably, the program device is a fuse device which can be blown by a laser beam applied from the outside.
Alternately, it is preferable that the program device is a fuse device which can be blown by a high voltage applied from the outside.
With such a configuration, even after package molding, a program can be entered from the outside.
Preferably, the plurality of internal lines include a first line in a high impedance state and a second line for shielding the first line.
With the configuration, the layout having increased noise resistance can be designed.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.